Excerpt:
"The Universal Scan Demo Board has 3 JTAG CPLDs in a JTAG chain. A Xilinx 9536, a Lattice 2032 and an Altera 3032...

To add a part to a screen, simply press the Add Device button, navigate your way down the BSDL list, and double click on the device you want. Universal Scan automatically builds me a 44 pin quad flatpack for that device.."

Excerpt:
" Monitoring pin activity by watching pins gets old pretty quick,so Universal Scan provides a bunch of virtual LEDs you can connect to the pins to help organize your testing. You can connect to whatever pins you want, change colors as you want. You can specify an LED or a latching LED, and most importantly, you can connect an LED to an input buffer,output buffer or tri-state buffer..."

Excerpt:
"Where boundary scan really shines is when you drop a device into EXTEST mode so you can manually control every scan-enabled pin on the device. With Universal Scan you can connect virtual switches to any of the three points in the I/O buffer, although you will usually only want to control the output and the tri-state signals..."

Excerpt:
"...we have a Xilinx 18V512 PROM in a 44 pin package and 2v40 FPGA in a 256 pin FPGA package.. we've added 4 virtual LEDS to monitor the input buffers of the clock signals on the FPGA design so that in a glance we can see that two of the four clocks are definitely connected to the pins under the BGA. Remember Universal Scan only scans the parts at a 10Hz rate, so you are not going to see a 200 Hz clock...what you will see is a blinking pin (virtual LED), which tells you there is activity at that pin. And let's face it, most of the time, when we put an o-scope probe on the pin, all we really want to know is if the pin is high, low or toggling.

That's what Universal Scan tells us. Its an activity indicator. Its simple, quick and intuitive."

Excerpt:
" In this example, we have a Motorola processor in a BGA package and a custom ASIC in a Quad flat pack package....quickly and simply with just a jtag download cable and a laptop. We can also see at a glance,
the oscillator is definitely driving the input buffer of the processor and that the crystal is definitely driving the input buffer of the custom ASIC. Because both of these parts are in SAMPLE/PRELOAD mode, we are able to monitor all of this activity without affecting the operation of the circuitry..."

Excerpt:
" ...Sometimes new designs don't always come up as easily as you'd like. It may be an issue with your board or your hardware scan chain, or you may have the wrong BSDL or the BSDL has errors in it. The good news is that both of these are easy to debug with Universal Scan's built in jtag debug and diagnostic tools... Its a good idea to run these diagnostics on all new boards..."

Excerpt:
"In this example, we have a flash device connected to this FPGA in the JTAG chain… To program that PROM, we specify the data file, set up the signal pins, bank selects, statics, options and algorithms…in this case, we have we have a data bus that is 8 bits wide, a PROM whose maximum possible width is 8 bits wide and is currently in an 8 bit mode, sitting at ADDR0…"

Excerpt:
" ..We are using a much larger flash device to show you how size affects programming time…this example has two 16 bit 8 MB Intel PROMS in parallel to form a 32 bit data bus….adding signals is easy - pick the signal you want to add, which device you want to add it to, and what pin you are going to hook it up to.."."

Excerpt:
" ..Programming SPI Flash devices with Universal Scan couldn't be easier - you just setup the SPI Flash Programmer, select a data file and hit PROGRAM! .."